Semiconductor element

ABSTRACT

In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the &lt;11-20&gt; direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

TECHNICAL FIELD

The present invention relates to a high-breakdown-voltage insulated gatesemiconductor device using silicon carbide, and more particularlyrelates to a MOS field effect transistor (MOSFET) that provides alarge-current switching device.

BACKGROUND ART

Silicon carbide (SiC) is a semiconductor with a higher hardness and awider band gap than silicon (Si) and applied to power devices,environmentally resistant devices, high-temperature operating devices,high-frequency devices, and other devices.

For example, MOSFETs as disclosed in Patent Document 1 that will bedescribed below are known as representative switching devices using SiC.FIGS. 14(a) and 14(b) are diagrams showing typical verticalaccumulation-mode MOSFETs using SiC. In a unit cell of a typicalvertical MOSFET, a source electrode is arranged in the middle of theunit cell. On the other hand, FIGS. 14(a) and 14(b) show the arrangementof electrodes with a gate electrode arranged in the middle. That is,FIGS. 14(a) and 14(b) show a joint between two unit cells. FIG. 14(a) isa plan view showing some of electrodes of MOSFETs when seen from above,and FIG. 14(b) is a cross-sectional view showing the MOSFETs taken alongthe line XI-XI shown in FIG. 14(a).

As shown in FIGS. 14(a) and 14(b), the known vertical accumulation-modeMOSFET comprises a semiconductor substrate 101 made of n⁺-type 4H—SiC,an n-type silicon carbide layer 102 formed on the semiconductorsubstrate 101 and made of n-type 4H—SiC, p-type well regions 103 formedin regions of the upper part of the n-type silicon carbide layer 102located at both sides of the joint between the two unit cells and dopedwith, for example, aluminum, a channel layer 104 formed on a region ofthe n-type silicon carbide layer 102 interposed between the two p-typewell regions 103 and the top surfaces of the two p-type well regions andmade of, for example, n-type 4H—SiC, source regions 105 formed in theupper parts of the p-type well regions 103 to come into contact with thelateral sides of the channel layer 104, respectively, and doped with,for example, nitrogen, a gate insulating film 106 formed on the channellayer 104 and respective parts of the source regions 105, a gateelectrode 107 formed on a part of the gate insulating film 106, sourceelectrodes 108 formed from on the top surface of the source regions 105to on respective parts of the n-type silicon carbide layer 102 locatedto the outermost lateral sides of the source regions 105, and a drainelectrode 109 formed on the back surface of the semiconductor substrate101.

The source electrodes 108 each have a structure in which it alsofunctions as base electrodes to which the p-type well regions 103 areelectrically connected.

In order to turn the MOSFET ON, a positive voltage is applied to thedrain electrode 109, the source electrodes 108 are grounded, and apositive voltage is applied to the gate electrode 107. In this way,switching operations of the MOSFET can be achieved.

When the MOSFET is thus turned ON, electrons serving as carriersinitially flow in the direction parallel to a substrate surface as shownin FIGS. 14(a) and 14(b). Thereafter, the electrons flow in thedirection perpendicular to the substrate surface as shown in FIG. 14(b).The arrows shown in FIGS. 14(a) and 14(b) show directions in whichelectrons serving as carriers travel. Current flows in the oppositedirections to these arrows. In this relation, the directions in whichelectrons travel in FIG. 14(a) should be noted. The source electrodes108 and the gate electrode 107 are arranged such that carriers travel inthe direction perpendicular to a substrate miscut direction A. The“miscut direction” indicates the direction within a miscut surfaceinclined at an angle of several degrees from the crystal plane andextending from a normal vector to the crystal plane toward a normalvector to the miscut surface. The reason why the electrodes are arrangedas described above will be described hereinafter with reference to FIG.15. FIG. 15 is a perspective view schematically showing the top surfaceand cross sections of a silicon carbide substrate.

The silicon carbide substrate shown in FIG. 15 has a substrate surfacemiscut by a predetermined angle to the (0001) plane. In FIG. 15, thesubstrate surface, i.e., the miscut surface is horizontally oriented.Typically, when an element is formed using a silicon carbide substrate,a miscut substrate to the (0001) plane is used. The reason for this isthat if a layer is formed by epitaxial growth on a substrate surfacemiscut by a predetermined angle to the (0001) plane, the polytype can beeasily controlled. For example, the surface miscut by approximately 8degrees from the 4H—SiC(0001) plane in the <11-20> direction (whichherein means 1120) is formed as the miscut surface.

However, when a high-temperature process, such as epitaxial growth andheat treatment for dopant activation, is applied to a substrate havingthe miscut surface as the substrate surface, the step-bunching isdeveloped at the substrate surface along the direction perpendicular tothe miscut direction. For example, when the miscut direction is the<11-20> direction, step bunches are formed to protrude along the <1-100>direction perpendicular to the <11-20> direction. The step bunches havea height of approximately 50 through 100 nm, leading to anisotropy inelectrical characteristics. The electron mobility in the miscutdirection (in the direction transverse to the step bunches) hasconventionally differed, for example, by one or more orders ofmagnitude, from that in the direction perpendicular to the miscutdirection (i.e., in the direction parallel to the step bunches).

In view of the above reason, in order to fabricate a semiconductordevice capable of passing a large amount of current, electrodes has beenrequired to be arranged such that current flows in the directionperpendicular to the miscut direction. When currents flow through thechannel layer 104 in a plurality of directions, electrodes need havebeen designed such that one of the plurality of directions in which thelargest amount of current flows is matched with the directionperpendicular to the miscut direction (for example, Patent Document 1).

Patent Document 1: Japanese Unexamined Patent Publication No.2001-144288

Patent Document 2: PCT/JP98/01185

DISCLOSURE OF INVENTION

Problems that the Invention is to Solve

As described above, the arrangement of elements has conventionally beendetermined based on the premise that the formation of step-bunchingincreases the electron mobility in the direction parallel to thestep-bunching and decreases the electron mobility in the directionperpendicular thereto. Even when no step-bunching is developed at thesurface of the substrate, crystal defects, such as stacking faults,exist in silicon carbide, and thus the electron mobility in thedirection parallel to the miscut direction has sometimes become smallerthan that in the direction perpendicular thereto. However, in somecases, the anisotropy in the direction of current travel is reversed. Inthis case, the electrical characteristics of elements have beendeteriorated.

It is an object of the present invention to provide a silicon carbidesemiconductor device with more excellent electrical characteristics bytaking a measure for solving the above problems.

Means of Solving the Problems

A semiconductor device according to a first aspect of the presentinvention comprises: a semiconductor substrate; a silicon carbide layerformed on the semiconductor substrate and having its top surfaceinclined at an angle of 10 degrees or less from a crystal plane in amiscut direction; a gate insulating film formed on the silicon carbidelayer; a gate electrode formed on the gate insulating film; a sourceelectrode formed on a part of the silicon carbide layer located to aside of the gate electrode; a drain electrode formed on the back surfaceof the semiconductor substrate; and a source region formed in a regionof the silicon carbide layer located at least under the sourceelectrode, wherein the longest of the edges of the source region extendsalong the direction perpendicular to the miscut direction in a planview.

In this way, the source region is arranged to allow current to flowalong the miscut direction, thereby improving electricalcharacteristics. Furthermore, the possibility that the currentanisotropy is reversed is eliminated. The reason for the above is asfollows. In the known art, step-bunching is developed in the directionperpendicular to the miscut direction of the silicon carbide layerduring high-temperature heat treatment, and the electron mobility alongthe direction parallel to the step-bunching has been large. On the otherhand, the semiconductor device of the present invention is formedthrough the step of heat treatment using a compound containing a group-Velement. This reduces the interface state density at the interfacebetween the gate insulating film and the silicon carbide layer, at whicha channel layer is formed, and improves the electron mobility along themiscut direction even when the step-bunching is developed at the topsurface of the silicon carbide layer. Therefore, the electron mobilityalong the miscut direction is likely to become higher than that in thedirection perpendicular to the miscut direction.

The semiconductor device of the first aspect may further comprise: awell region of a second conductivity type formed in a part of thesilicon carbide layer located on a lateral side of the source region andunder the source region; and a base electrode electrically connected tothe well region.

A direction extending along the direction perpendicular to the miscutdirection may be a direction at an inclination of 5 degrees or less fromthe direction perpendicular to the miscut direction. Therefore, highelectron mobility can be achieved.

A channel layer may be formed in a region of the silicon carbide layerlocated under the gate insulating film.

The channel region may have a multilayer structure including a firstsilicon carbide layer of at least one layer and a second silicon carbidelayer of at least one layer having a higher first-conductivity-typedopant concentration and a smaller thickness than the first siliconcarbide layer. In this case, higher electron mobility can be achieved.

When the electron mobility through the silicon carbide layer is largerin the direction perpendicular to the crystal plane than in in-planedirections of the crystal plane, the present invention is effective.

The silicon carbide layer may be 4H—SiC

The top surface of the silicon carbide layer may be a plane inclinedfrom the (0001) plane in the <11-20> direction.

The top surface of the silicon carbide layer may be a plane inclinedfrom the (0001) plane in the <1-100> direction.

When the gate insulating film is formed by thermally oxidizing the upperpart of the silicon carbide layer and subjecting the resultant upperpart thereof to heat treatment in an atmosphere containing a compoundinclusive of a group-V element, the interface state density can bereduced, resulting in the increased electron mobility in the miscutdirection.

When the compound inclusive of the group-V element is nitric oxide(N_(x)O_(y)(x, y=1, 2, . . . )), a large effect can be obtained.

A maximum nitrogen concentration is preferably 1×10²⁰ cm⁻³ through1×10²² cm⁻³ both inclusive at the interface between the silicon carbidelayer and the gate insulating film, i.e., at the interface between thechannel layer and the gate insulating film. In this case, the interfacedensity within the potential range near each of band edges can bereduced enough. Therefore, independently of whether or not thestep-bunching is developed between the top surface of the siliconcarbide layer and a gate oxide film, an excellent interface is formedtherebetween.

Even when the gate electrode is formed by subjecting the upper part ofthe silicon carbide layer to heat treatment in an atmosphere containinga compound inclusive of a group-V element, an excellent interfacebetween the gate insulating film and the silicon carbide layer can beachieved. In particular, the gate insulating film formed by heattreatment in an atmosphere containing the nitric oxide also workseffectively to the present invention.

When the silicon carbide layer contains dopants of the firstconductivity type and the semiconductor element of the first aspectcomprises: the source electrode formed on a part of the silicon carbidelayer located to a side of the gate electrode; the drain electrodeformed on the back surface of the semiconductor substrate; and thesource region of a first conductivity type formed in a region of thesilicon carbide layer located at least under the source electrode andcoming into contact with the channel layer; a well region of a secondconductivity type formed in a part of the silicon carbide layer to coverone lateral side and the bottom of the source region; and a baseelectrode electrically connected to the well region, high electronmobility can be achieved in a vertical MOSFET.

The source electrode may be formed using the same conductive film as thebase electrode.

The gate electrode may be formed to have a shape in which polygons arehollowed out in a plan view. In this case, the longest of the edges ofthe hollowed polygons preferably extend along the directionperpendicular to the miscut direction.

In this case, the source electrode may be formed in the shape ofpolygons in a plan view, and the gate electrode may be formed so as tobe located apart from the source electrode and surround the lateralsides of the source electrode.

The gate electrode may be formed in the shape of a polygon in a planview. In this case, the longest of the edges of the polygon preferablyextends along the direction perpendicular to the miscut direction.

In this case, in a plan view, the source electrode may be formed to havea comb shape including a plurality of first rectangular parts arrangedin stripes and a first connection part through which the respective oneends of the plurality of first rectangular parts are connected to oneanother, and the gate electrode may be formed to have a comb shapeincluding a plurality of striped second rectangular parts arrangedalternately with the plurality of first rectangular parts and a secondconnection part through which the respective one ends of the pluralityof second rectangular parts are connected to one another.

Herein, a “polygon” and a “comb shape” include shapes having roundedcorners or curved edges. When the source region has, for example, anelliptical shape, “the longest of the edges of the source region extendsalong the direction perpendicular to the miscut direction” means thatthe major axis of the elliptical shape extends along the directionperpendicular to the miscut direction.

A semiconductor device according to a second aspect of the presentinvention comprises: a semiconductor substrate; a silicon carbide layerformed on the semiconductor substrate and having its top surfaceinclined at an angle of 10 degrees or less from a crystal plane in amiscut direction; a gate insulating film formed on the silicon carbidelayer; a gate electrode formed on the gate insulating film; a sourceelectrode formed on a part of the silicon carbide layer located to oneside of the gate electrode; a drain electrode formed on a part of thesilicon carbide layer located to the other side of the gate electrode;and source/drain regions formed apart from each other in regions of thesilicon carbide layer located at least under the source and gateelectrodes, wherein the opposed two of the edges of the source/drainregions extend along the direction perpendicular to the miscut directionin a plan view.

In this way, the source/drain regions are arranged to allow current toflow along the miscut direction, thereby improving electricalcharacteristics. The reason for the above is as follows. In the knownart, step-bunching is developed in the direction perpendicular to themiscut direction of the silicon carbide layer during high-temperatureheat treatment, and the electron mobility along the direction parallelto the step-bunching has been large. On the other hand, thesemiconductor element of the present invention is formed through thestep of heat treatment using a compound containing a group-V element.This reduces the state density at the interface between the gateinsulating film and the silicon carbide layer, at which a channel layeris formed, and improves the electron mobility along the miscut directioneven when the step-bunching is developed at the top surface of thesilicon carbide layer. Therefore, the electron mobility along the miscutdirection is likely to become higher than that in the directionperpendicular to the miscut direction.

The semiconductor device of the second aspect may further comprise: abase region formed in the silicon carbide layer and containing dopantsof a first conductivity type; and a base electrode electricallyconnected to the base region.

The gate electrode may be formed in the shape of a polygon. In thiscase, the longest of the edges of the polygon preferably extends alongthe direction perpendicular to the miscut direction.

A direction extending along the direction perpendicular to the miscutdirection is a direction at an inclination of 5 degrees or less from thedirection perpendicular to the miscut direction. Therefore, a highelectron mobility can be achieved.

A channel layer may be formed in a region of the silicon carbide layerlocated under the gate insulating film.

The channel region may have a multilayer structure including a firstsilicon carbide layer of at least one layer and a second silicon carbidelayer of at least one layer having a higher first-conductivity-typedopant concentration and a smaller thickness than the first siliconcarbide layer. In this case, higher electron mobility can be achieved.

When the electron mobility through the silicon carbide layer is largerin the direction perpendicular to the crystal plane than in in-planedirections of the crystal plane, the present invention is effective.

The silicon carbide layer may be 4H—SiC.

The top surface of the silicon carbide layer may be a plane inclinedfrom the (0001) plane in the <11-20> direction.

The top surface of the silicon carbide layer may be a plane inclinedfrom the (0001) plane in the <1-100> direction.

When the gate insulating film is formed by thermally oxidizing the upperpart of the silicon carbide layer and subjecting the resultant upperpart thereof to heat treatment in an atmosphere containing a compoundinclusive of a group-V element, the interface state density can bereduced, resulting in the increased electron mobility in the miscutdirection.

When the compound inclusive of the group-V element is nitric oxide(N_(x)O_(y)(x y=1, 2, . . . )), a large effect can be obtained.

A maximum nitrogen concentration is preferably 1×10²⁰ cm⁻³ through1×10²² cm⁻³ both inclusive at the interface between the silicon carbidelayer and the gate insulating film, i.e., at the interface between thechannel layer and the gate insulating film. In this case, the interfacedensity within the potential range near each of band edges can bereduced enough. Therefore, independently of whether or not thestep-bunching is developed between the top surface of the siliconcarbide layer and a gate oxide film, an excellent interface is formedtherebetween.

The source electrode may be formed using the same film as the baseelectrode.

Effect of the Invention

According to the semiconductor device of the present invention, when theelectron mobility reduced due to step-bunching and other unfavorableinterface states is improved, this can provide more excellent electricalcharacteristics than those of a known structure of a semiconductordevice.

BRIEF DESCRIPTION OF DRAWINGS

[FIG. 1] FIGS. 1(a) and 1(b) are cross-sectional views showing a jointbetween two unit cells of typical vertical accumulation-mode MOSFETsusing a silicon carbide layer in a first embodiment.

[FIG. 2] FIGS. 2(a) through 2(c) are cross-sectional views showing aprocedure for forming a SiC-oxide layered structure.

[FIG. 3] FIG. 3 is a graph showing the nitrogen concentration profilewhere the nitrogen concentration in the thickness direction of a V-groupelement containing oxide layer 22 formed according to a productionmethod of the first embodiment was measured by SIMS.

[FIG. 4] FIGS. 4(a) and 4(b) are graphs showing an interface statedensity calculated using a High-Low method based on data shown in FIG.3.

[FIG. 5] FIG. 5 is a plan view showing the relationship between adirection in which carriers travel and the arrangement of elements inthe semiconductor devices shown in FIG. 1.

[FIG. 6] FIG. 6(a) is a diagram showing, by vectors, a direction inwhich electrons travel and a length over which the electrons travelthrough a silicon carbide substrate having a (0001) plane as its topsurface, and FIG. 6(b) is a diagram showing, by vectors, a direction inwhich electrons travel and a length over which the electrons travelthrough a silicon carbide substrate having, as its top surface, a planeinclined at an angle θ from the (0001) plane.

[FIG. 7] FIGS. 7(a) and 7(b) are diagrams showing the configuration ofMOSFETs when gate and source electrodes are arranged in comb form.

[FIG. 8] FIGS. 8(a) and 8(b) are diagrams showing the configuration ofMOSFETs when rectangular unit cells are arranged.

[FIG. 9] FIGS. 9(a) and 9(b) are diagrams showing the configuration ofMOSFETs when hexagonal unit cells are arranged.

[FIG. 10] FIG. 10 is a cross-sectional view showing the configuration ofvertical inversion-type MOSFETs.

[FIG. 11] FIGS. 11(a) and 11(b) are cross-sectional views showingtypical lateral accumulation-mode MOSFETs using a silicon carbide layeraccording to a second embodiment.

[FIG. 12] FIG. 12 is a plan view showing the relationship between adirection in which carriers travel and the configuration of elements inthe semiconductor device shown in FIG. 11(b).

[FIG. 13] FIG. 13 is a cross-sectional view showing the structure oflateral inversion-type MOSFETs.

[FIG. 14] FIGS. 14(a) and 14(b) are diagrams showing a joint between twounit cells of typical vertical accumulation-mode MOSFETs using SiC.

[FIG. 15] FIG. 15 is a perspective view schematically showing the topsurface and cross section of a silicon carbide substrate.

DESCRIPTION OF NUMERALS

-   1A interlayer insulating film-   1B upper interconnect electrode-   7C base electrode-   10 vertical accumulation-mode MOSFET-   11 semiconductor substrate-   12 n-type silicon carbide layer-   13 p-type well regions-   14 channel layer-   15 n-type source regions-   16 gate insulating film-   17 gate electrode-   18 source electrodes-   19 drain electrode-   20 SiC substrate-   21 oxide layer-   30 chamber-   31 vacuum pump-   60 vertical inversion-type MOSFET-   70 lateral accumulation-mode MOSFET-   71 semiconductor substrate-   72 p-type silicon carbide layer-   74 channel layer-   75 d drain region-   75 s source region-   76 gate insulating film-   77 gate electrode-   78 source electrode-   79 drain electrode-   90 lateral inversion-type MOSFET-   101 semiconductor substrate-   102 n-type silicon carbide layer-   103 p-type well regions-   104 channel layer-   105 source regions-   106 gate insulating film-   107 gate electrode-   108 source electrodes-   109 drain electrode

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described hereinafter withreference to the drawings.

Embodiment 1

FIGS. 1(a) and 1(b) are cross-sectional views showing a joint betweentwo unit cells of typical vertical accumulation-mode MOSFETs using asilicon carbide layer in a first embodiment. FIG. 1(a) is a plan viewshowing some of electrodes of the MOSFETs, and FIG. 1(b) is across-sectional view taken along the line I-I in FIG. 1(a).

As shown in FIGS. 1(a) and 1(b), a semiconductor device of thisembodiment has an n⁺-type 4H—SiC(0001) semiconductor substrate 11. Thesemiconductor substrate 11 has a surface miscut by approximately 8degrees in the <11-20> direction, and its resistivity is approximately0.02 Ωcm². An n-type 4H—SiC(0001) silicon carbide layer 12 is formed onthe semiconductor substrate 11 to have a thickness of approximately 15μm and doped with nitrogen at a concentration of 3×10¹⁵ cm⁻³. The n-typesilicon carbide layer 12 is formed on the semiconductor substrate 11 byepitaxial growth, and the influence of the semiconductor substrate 11causes the top surface of the n-type silicon carbide layer 12 to have anoff angle in the <11-20> direction.

P-type well regions 13 are formed in regions of the upper part of then-type silicon carbide layer 12 located to both lateral sides of thejoint between the two unit cells in the following manner: the n-typesilicon carbide layer 12 is doped with, for example, aluminum at aconcentration of approximately 2×10¹⁸ cm⁻³ to a depth of approximately0.8 μm, and then the aluminum-doped silicon carbide layer 12 is annealedat a high temperature of approximately 1700 degrees.

A channel layer 14 of n-type 4H—SiC is formed to extend over a region ofthe top surface of the n-type silicon carbide layer 12 interposedbetween the two p-type well regions and the top surfaces of the twop-type well regions. In this embodiment, the channel layer 14 is aδ-doped layer obtained by alternately stacking undoped layers and dopedlayers containing n-type dopants at a concentration of approximately5×10¹⁷ cm⁻³. The channel layer 14 has a thickness of approximately 0.2μm.

Source regions 15 are formed in the upper parts of the p-type wellregions 13 to come into contact with the lateral sides of the channellayer 14 in the following manner: the p-type well regions 13 are dopedwith, for example, nitrogen at a concentration of approximately 1×10¹⁹cm⁻³ to a depth of approximately 0.3 μm, and then the nitrogen-dopedp-type well regions 13 are annealed at a high temperature ofapproximately 1700 degrees.

Basically, source regions 15 are formed by doping respective parts ofthe p-type well regions with n-type dopants, and a MOSFET 10 is aso-called double implantation MOSFET (DIMOSFET). In FIG. 1, the sourceregions are configured such that the channel layer is interposedtherebetween. A channel layer is deposited on the formed p-type wellregions and furthermore n-type dopants are implanted into the n-typesilicon carbide layer 12 from above the channel layer, thereby formingsource regions. However, a semiconductor device may be achieved, forexample, by forming p-type well regions and source regions and then achannel layer.

A gate insulating film 16 with a thickness of approximately 60 nm isformed on the channel layer 14 and respective parts of the sourceregions 15 in the following manner: the respective upper parts of thesource regions 15 and the channel layer 14 are thermally oxidized andthen subjected to heat treatment under an atmosphere containing aV-group element. A method for this heat treatment will be describedbelow.

A gate electrode 17 of aluminum is formed on the gate insulating film16.

Source electrodes 18 of nickel are formed from on the source regions 15to on respective parts of the n-type silicon carbide layer 12 located tothe outermost lateral sides of the source regions 15 in the followingmanner: a nickel film is formed and then subjected to heat treatment ata temperature of approximately 1000 degrees. This heat treatment allowsthe source electrodes 18 to make ohmic contact with the source regions15. The source electrodes 18 function also as base electrodeselectrically connected to the p-type well regions 13. In order to reducethe electrical resistance between the source electrodes 18 and thep-type well regions 13, p⁺-type ion implantation regions may be formedby implanting ions of aluminum into respective parts of the p-type wellregions 13 located at their interfaces with the source electrodes 18 ata higher concentration than that in the respective other parts thereof.

A drain electrode 19 of nickel is formed on the back surface of thesemiconductor substrate 11 in the following manner: a nickel film isformed and then subjected to heat treatment at a temperature ofapproximately 1000 degrees. This heat treatment allows the drainelectrode 19 to make ohmic contact with the semiconductor substrate 11.

The gate electrode 17 is covered with an interlayer insulating film 1A,and the interlayer insulating film 1A and the source electrodes 18 arecovered with an upper interconnect electrode 1B.

In order to turn the MOSFET 10 of this embodiment ON, a positive voltageis applied to the drain electrode 19, the source electrodes 18 aregrounded, and a positive voltage is applied to the gate electrode 17. Inthis way, switching operations of the MOSFET 10 can be achieved.

When the MOSFET 10 is thus turned ON, electrons serving as carriersinitially flow in the direction parallel to the substrate surface asshown in FIGS. 1(a) and 1(b). In this relation, unlike the known art, inthis embodiment, electrons flow in the direction parallel to the offcutdirection A. Thereafter, the electrons flow in the directionperpendicular to the substrate surface as shown in FIG. 1(b). The arrowsshown in FIGS. 1(a) and 1(b) show directions in which electrons servingas carriers travel. Current flows in the opposite directions to thesearrows.

A method in which the gate insulating film 16 is formed and thensubjected to heat treatment will be described in detail with referenceto the drawings. This method is disclosed in Japanese Patent ApplicationNos. 2003-350244 and 2004-271321 previously filed by the presentapplicant. The contents of the above-described applications areincorporated herein by reference.

FIGS. 2(a) through 2(c) are cross-sectional views showing a procedurefor forming a SiC-oxide layered structure. Although in this embodimentnitrogen is used as a V-group element, any other V-group element, suchas phosphorus (P) and arsenic (As), may be used.

First, in the process step shown in FIG. 2(a), a SiC substrate 20 thatis a 4H—SiC(0001) substrate is prepared. The upper part of the SiCsubstrate 20 (a part of the SiC substrate 20 located above the brokenline shown in FIG. 2(a)) is a 4H—SiC(0001) layer formed by epitaxialgrowth. The principal surface of the SiC substrate 20 (an epitaxiallygrown SiC layer) is smoothed by MCP (mechano-chemical polishing) suchthat the difference in surface levels (maximum surface roughness Rmax)become 10 nm or less. However, this smoothing process is not necessarilyrequired.

Next, in the process step shown in FIG. 2(b), the SiC substrate 20 isplaced in a chamber 30 and heated under an oxidizing atmosphere, therebyforming an oxide layer 21 (primarily containing SiO₂) on the SiCsubstrate 20 to have an average thickness of approximately 60 nm. Inthis case, an oxidizing temperature is 1000° C. or more, preferably 1050through 1300° C. In order to produce an oxidizing atmosphere, a gascontaining at least one of oxygen and water vapor need be allowed toflow through the chamber 30. Thereafter, the oxide layer 21 is annealedin an inert gas atmosphere (Ar, N₂, He, Ne, or other gases) at atemperature of 1000° C. or more (for example, 1000 through 1150° C.).The oxide layer 21 is densified in advance by this annealing process.

Next, in the process step shown in FIG. 2(c), the SiC substrate 20 ismoved into another chamber 30 having an exclusion device (not shown) anda vacuum pump 31 serving as a pressure reducer. Then, a NO gas (or a gascontaining a V-group element other than nitrogen (e.g., phosphorus (P))is introduced into the chamber 30 at a flow rate of 500 (ml/min) whilethe inside pressure of the chamber 30 is reduced by the vacuum pump 31to about 150 Torr (2.0×10⁴ Pa), and the inside of the chamber 30 isheated to a temperature sufficient for nitrogen (or a V-group elementother than nitrogen) to be diffused into the oxide layer 21 (e.g., about1150° C.). Under the reduce pressure condition, the oxide layer 21 isexposed to the V-group element containing gas, such as nitrogen, wherebya V-group element, such as nitrogen, is diffused into the oxide layer21. As a result, a denser V-group element containing oxide layer 22having a large relative dielectric constant is obtained. The exposure isperformed for a time period which is sufficient for forming the denseV-group element containing oxide layer 22 and sufficient for obtainingimproved characteristics of the V-group element containing oxide layer22 (e.g., 1 hour). After the above-mentioned process steps, heattreatment is completed.

FIG. 3 is a graph showing the nitrogen concentration profile where thenitrogen concentration in the thickness direction of the V-group elementcontaining oxide layer 22 formed according to the production method ofthis embodiment was measured by SIMS. More particularly, FIG. 3 showsthe extracted concentration distribution of the peak portion (regionnear the SiO₂—SiC interface). The data shown in FIG. 3 was obtained byquantitating nitrogen in the SiO₂—SiC interface with CsN¹⁴⁷. As shown inFIG. 3, the half-width of the peak portion was 3 nm, from which it isseen that nitrogen was introduced into a very narrow area with highconcentration.

FIGS. 4(a) and 4(b) show the interface state density calculated usingthe High-Low method based on the data shown in FIG. 3. In the graphs ofFIGS. 4(a) and 4(b), the horizontal axis indicates the potentialdifference from valence band Ev (E-Ev (eV)), and the vertical axisindicates interface state density Dit (cm⁻²eV⁻¹). In the case where thecarrier in a MISFET is an electron, the interface state which functionsas a trap is an interface state in the potential range near theconduction band edge (E-Ev=2.95 eV to 3.05 eV). In the case where thecarrier is a hole, the interface state which functions as a hole trap isan interface state in the potential range near the valence band edge(E-Ev=0.3 eV to 0.4 eV). However, as shown in FIGS. 4(a) and 4(b), inthis embodiment, the interface state density of 1×10¹² cm⁻²·eV⁻¹ orlower was obtained in the potential range near each band edge. Theaverage nitrogen concentration in the entire V-group element containingoxide layer 22 was 8.3×10¹⁹ cm⁻³.

Thus, when a V-group element, such as nitrogen, is contained in theV-group element containing oxide layer 22, the interface state densitywhich functions as a carrier trap is decreased, and accordingly, thecarrier mobility is improved.

Especially because the maximum value of the nitrogen concentration inthe lower part of the V-group element containing oxide layer 22 is equalto or higher than 1×10²⁰ cm⁻³ and equal to or lower than 1×10²² cm⁻³,the effect of improving the relative dielectric constant and the effectof decreasing the interface state density are significantly large.

Next, the arrangement of the semiconductor devices of this embodimentwill be described while being compared with that in the known art.

In the known art, as shown in FIG. 14, step-bunching is developed at thetop surface of a substrate by the influence of high-temperature heattreatment for activating dopants ion-implanted into a layer. Since thestep-bunching is developed along the direction perpendicular to themiscut direction, the arrangement of electrodes or other elements hasconventionally been determined such that more carriers flow in thedirection perpendicular to the miscut direction.

On the other hand, in this embodiment, elements are arranged such thatmore carriers flow substantially parallel to the miscut direction. FIG.5 is a plan view showing the relationship between the direction in whichcarriers travel and the arrangement of elements in the semiconductordevices shown in FIG. 1. In FIG. 5, the gate electrode 17, the sourceelectrodes 18 and some other elements are not shown, and only the n-typesilicon carbide layer 12, the p-type well regions 13 and the n-typesource regions 15 are shown. Although the channel layer 14 is not shown,the channel layer 14 is located on diagonally shaded regions of thep-type well regions 13. In a vertical MOSFET as shown in FIG. 5,carriers flow from the source regions 15 toward the n-type siliconcarbide layer 12. Elements are arranged such that the direction in whichthe carriers flow becomes substantially parallel to the miscutdirection.

—Principle on which the Electron Mobility Increases in the MiscutDirection—

The known semiconductor device has the following anisotropy: theelectron mobility is larger in the direction perpendicular to the miscutdirection than in the direction parallel thereto. On the other hand, inthe semiconductor device of this embodiment, this anisotropy isreversed. The reason for this is that in this embodiment, heat treatmentis performed using a gas containing nitrogen and oxygen, therebyreducing the interface state density at the interface between a siliconcarbide layer and a gate insulating film and improving the electronmobility along the miscut direction. The reason why the electronmobility of the silicon carbide substrate is large in the cut-offdirection will be examined hereinafter.

FIG. 6(a) is a diagram showing, by vectors, a direction in whichelectrons travel and a length over which the electrons travel through asilicon carbide substrate having a (0001) plane as its top surface. InFIG. 6(a), a vector parallel to the (0001) plane (designated crystalplane S) and the paper is designated as a vector a, a vector parallel tothe (0001) plane but perpendicular to the paper is designated as avector b, and a vector perpendicular to the (0001) plane is designatedas a vector c.

In this case, the electron mobility of the silicon carbide layer whosetop surface is the (0001) plane becomes larger in the directionperpendicular to the substrate surface than in in-plane directions ofthe substrate. More particularly, the vector c shown in FIG. 6(a) islarger than the vectors a and b. The vectors a and b have the samelength.

Next, the case where the silicon carbide substrate is a miscut substratewill be examined. FIG. 6(b) is a diagram showing, by vectors, adirection in which electrons travel and a length over which theelectrons travel through a silicon carbide substrate having, as its topsurface, a plane inclined at an angle θ from the (0001) plane.

In FIG. 6(b), each of the vectors a and c are broken down into a vectorextending along the miscut direction and a vector extending along thedirection perpendicular to the miscut direction. The vectorscorresponding to the vector a are designated as vectors a1 and a2, andthe vectors corresponding to the vector c are designated as c1 and c2.In this case, when a vector indicating the electron mobility in themiscut direction is designated as a vector d, the vector d is expressedby the sum of the vectors a1 and c1.

Since in this embodiment the vector c is larger than the vector a, thevector d becomes larger than the vector a. On the other hand, since thevector b is perpendicular to the miscut direction, the electron mobilityin the vector-b direction does not vary between when the top surface ofthe silicon carbide layer is the (0001) plane and when it is a miscutsurface. Since the vectors a and b have the same length, the vector d isobviously larger than the vector b.

In view of the above, the electron mobility (vector d) in the miscutdirection becomes larger than that (vector b) in the directionperpendicular to the miscut direction.

As a matter of course, even when vectors indicating directions otherthan the vectors b and d are taken into account, it is obvious that theelectron mobility in the miscut direction becomes largest within themiscut substrate surface.

The electron mobility in the miscut direction is improved by asynergistic effect resulting from the combination of the above-mentionedeffect of the vectors and the effect of reducing the interface statedensity at the interface between the silicon carbide layer and the gateinsulating film by subjecting the silicon carbide layer to heattreatment using a gas containing nitrogen and oxygen.

EXAMPLE OF THE ARRANGEMENT OF ELECTRODES

Shown in FIG. 1 is an example in which current is allowed to flow onlyalong the direction parallel to the miscut direction A at the jointbetween the two unit cells. However, actually, current is allowed toflow along a plurality of directions in many vertical semiconductordevices. In this case, elements are arranged such that one of theplurality of directions along which the largest amount of current flowsbecomes parallel to the miscut direction. The structure of the verticalsemiconductor device will be described hereinafter.

First Arrangement Example

In vertical MOSFETs, a source electrode 18 and a gate electrode 17 maybe arranged in stripes (or in comb form). This case will be describedwith reference to FIGS. 7(a) and 7(b).

FIGS. 7(a) and 7(b) are diagrams showing the configuration of MOSFETswhen the gate and source electrodes are arranged in comb form. FIG. 7(a)shows the configuration of a gate electrode 17 and a source electrode18, and FIG. 7(b) shows the configuration of an n-type silicon carbidelayer 12, p-type well regions 13 and n-type source regions 15. As shownin FIG. 7(a), a plurality of rectangular parts of the source electrode17 are arranged in stripes. Respective one ends of the plurality ofrectangular parts of the source electrode 17 are electrically connectedto one another by making contact with a connection part of the sourceelectrode 17 extending perpendicularly to the direction along which therectangular parts thereof extend. A plurality of rectangular parts ofthe gate electrode 18 are arranged in stripes alternately with therectangular parts of the source electrode 17. Respective one ends of theplurality of rectangular parts of the gate electrode 18 are electricallyconnected to one another by making contact with a connection part of thegate electrode 18 extending perpendicularly to the direction along whichthe rectangular parts thereof extend. A channel region is arranged indiagonally shaded regions shown in FIG. 7(b). In this case, thedirections in which carriers travel are given two directions, i.e., thedirections A and B. The channel region primarily extends along thedirection perpendicular to the direction A. In view of the above,elements are arranged such that the width W1 of the channel regionthrough which current is allowed to flow along the direction A is equalto or larger than the other width W2 of the channel region. The longestedges of each n-type source region 15 are also oriented perpendicularlyto the miscut direction A.

Second Arrangement Example

A vertical MOSFET is arranged for each of polygonal unit cells, in eachof which the lateral sides of a source electrode may be surrounded by agate electrode. This case will be described with reference to FIGS. 8(a)and 8(b).

FIGS. 8(a) and 8(b) are diagrams showing the configuration of verticalMOSFETs when rectangular unit cells are arranged. FIG. 8(a) shows theconfiguration of a gate electrode 17 and a source electrode 18, and FIG.8(b) shows the configuration of an n-type silicon carbide layer 12,p-type well regions 13 and n-type source regions 15. Channel regions arearranged in diagonally shaded regions shown in FIG. 8(b).

In this case, the directions in which carriers travel are given twodirections, i.e., the directions A and B. When the longitudinaldirection of each unit cell is set perpendicularly to the direction A,parts of each channel region extending along the direction perpendicularto the direction A become longer than parts of the channel regionextending along the direction parallel thereto. In view of the above, asshown in FIG. 8(b), elements are arranged such that the width W1 of thechannel region through which current is allowed to flow along thedirection A is equal to or larger than the other width W2 thereof. Thelongest edges of each n-type source region 15 are also orientedperpendicularly to the miscut direction A.

Although in this example a case where the unit cell is rectangular wasdescribed, the unit cell may have a polygonal shape, such as aparallelogram or a rhombus. FIGS. 9(a) and 9(b) are diagrams showing theconfiguration of vertical MOSFETs when hexagonal unit cells arearranged. FIG. 9(a) shows the configuration of a gate electrode 17 andsource electrodes 18, and FIG. 9(b) shows the configuration of a n-typesilicon carbide layer 12, p-type well regions 13 and n-type sourceregions 15. Channel regions are arranged in diagonally shaded regionsshown in FIG. 9(b).

In this case, there are primarily three directions in which carrierstravel, i.e., directions A, C and D. When the longest two of the edgesof each hexagonal unit cell are arranged perpendicularly to thedirection A, parts of the channel regions extending along the directionperpendicular to the direction A become longer than parts thereofextending along the direction perpendicular to the directions C and D.In view of the above, as shown in FIG. 9(b), elements are arranged suchthat the width W1 of each of parts of the channel regions through whichcurrent flows along the direction A becomes equal to or larger than thewidth W2 of each of the other parts of the channel regions through whichcurrent flows along the other directions. The longest edges of eachn-type source region 15 are also oriented perpendicularly to the miscutdirection A.

The method described in this embodiment can be applied not only to thecase where the δ-doped layer is used as the channel layer but also tothe case where the channel layer is a usual n-type dopant layer.

Furthermore, the method described in this embodiment can also be appliedto a vertical inversion-type MOSFET 60. FIG. 10 is a cross-sectionalview showing the configuration of vertical inversion-type MOSFETs.Unlike FIG. 1, in FIG. 10, the channel layer (shown in FIG. 1) is notformed. Since the other structure of each MOSFET is the same as that inFIG. 1, a description thereof is not given.

Embodiment 2

FIGS. 11(a) and 11(b) are cross-sectional views showing typical lateralaccumulation-mode MOSFETs using a silicon carbide layer according to asecond embodiment. FIG. 11(a) is a plan view showing some of electrodesof the MOSFETs when seen from above, and FIG. 11(b) is a cross-sectionalview taken along the line VII-VII in FIG. 11(a).

As shown in FIGS. 11(a) and 11(b), a semiconductor device of thisembodiment has a semi-insulating 4H—SiC(0001) semiconductor substrate71. The semiconductor substrate 71 has a surface miscut by approximately8 degrees in the <11-20> direction. A 4H—SiC(0001) p-type siliconcarbide layer 72 is formed on the semiconductor substrate 71 to have athickness of approximately 5 μm and doped with aluminum at aconcentration of 5×10¹⁵ cm⁻³.

An n-type channel layer 74 is formed in the middle region of the upperpart of the p-type silicon carbide layer 72. In this embodiment, thechannel layer 74 is a δ-doped layer obtained by alternately stackingundoped layers and doped layers containing n-type dopants at aconcentration of approximately 5×10¹⁷ cm⁻³. The channel layer 74 has athickness of approximately 0.2 μm.

A source region 75 s and a drain region 75 d are formed in regions ofthe p-type silicon carbide layer 72 located to both sides of the channellayer 74 in the following manner: for example, the p-type siliconcarbide layer 72 is doped with nitrogen at a concentration ofapproximately 1×10¹⁹ cm⁻³ to a depth of about 0.3 μm, and then thenitrogen-doped p-type silicon carbide layer 72 is annealed at a hightemperature of about 1700 degrees.

In principle, the source region 75 s and the drain region 75 d areformed by doping parts of a p-type well region with n-type dopants. AMOSFET 70 is a so-called double implantation MOSFET (DIMOSFET).

In FIGS. 11(a) and 11(b), the channel layer is sandwiched between thesource and drain regions. A p-type well region is formed, then a channellayer is deposited thereon, and furthermore the p-type well region isdoped with n-type dopants from above the channel layer, thereby formingsource and drain regions. A semiconductor device may be achieved byforming a p-type well region and source and drain regions and then achannel layer.

A gate insulating film 76 with a thickness of about 60 nm is formed overthe channel layer 74 and respective one lateral end parts of the sourceregion 75 s and the drain region 75 d in the following manner: therespective upper parts of the channel layer 74, the source region 75 sand the drain region 75 d are thermally oxidized, and then the thermallyoxidized upper parts thereof are subjected to heat treatment in anatmosphere containing a V-group element.

A gate electrode 77 of aluminum is formed on part of the gate insulatingfilm 76.

A source electrode 78 of nickel is formed on part of the source region75 s, and a drain electrode 79 of nickel is formed on part of the drainregion 75 d. A source electrode 78 and a drain electrode 79 are formedin the following manner: a nickel film is formed, and then the nickelfilm is subjected to heat treatment at a temperature of about 1000degrees. This heat treatment allows the source region 75 s and the drainregion 75 d to make ohmic contact with the source electrode 78 and thedrain electrode 79, respectively.

A base electrode 7C is formed on a region of the p-type silicon carbidelayer 72 located to the outer lateral side of the source region 75 s toelectrically connect the p-type silicon carbide layer 72 to the outside.In order to reduce the electrical resistance between the base electrode7C and the p-type silicon carbide layer 72, a p⁺-type ion implantationregion may be formed by implanting ions of aluminum into a part of thep-type silicon carbide layer 72 located at the interface therebetween ata higher concentration than that in the other part thereof. Furthermore,the source electrode 78 and the base electrode 7C may be electricallyjoined with each other or made of the same conductive film.

In order to turn the MOSFET 70 of this embodiment ON, a positive voltageis applied to the drain electrode 79, the source electrode 78 and thebase electrode 7C are grounded, and a positive voltage is applied to thegate electrode 77. In this way, switching operations of the MOSFET 70can be achieved.

When the MOSFET 70 is thus turned ON, electrons serving as carriers flowfrom the source region 75 s toward the drain region 75 d in thedirection parallel to the substrate surface as shown in FIGS. 11(a) and11(b). In this relation, unlike the known art, in this embodiment,electrons flow in the direction parallel to the miscut direction A. Theconfiguration of semiconductor devices of this embodiment will bedescribed below with reference to FIG. 12. FIG. 12 is a plan viewshowing the relationship between a direction in which carriers traveland the configuration of elements in the semiconductor devices shown inFIG. 11(b). In FIG. 12, the gate electrode 77, the source electrode 78,the drain electrode 79, and other elements are not shown, and only thep-type silicon carbide layer 72, the n-type source region 75 s and then-type drain region 75 d are shown. Although the channel layer 74 is notshown, it is located on a diagonally shaded region of the p-type siliconcarbide layer 72. As shown in FIG. 12, in a lateral MOSFET, carrierstravel in the direction from the source region 75 s toward the drainregion 75 d. Elements are arranged such that this direction becomessubstantially parallel to the miscut direction A.

In many lateral elements, current flowing therethrough isunidirectional. In some lateral elements, however, current flows in twoor more directions. In this case, elements are arranged such that thedominating current flows in the direction parallel to the miscutdirection A of the substrate. More particularly, elements are arrangedsuch that one W1 of the widths of the channel region across whichcurrent flows through the channel region along the direction A becomesequal to or larger than the other width or widths thereof. In otherwords, elements are arranged such that the respective opposed edges ofthe source region 75 s and the drain region 75 d (the respective edgesthereof coming into contact with the channel layer 74) becomeperpendicular to the miscut direction A.

The method described in this embodiment can be applied to not only thecase where a δ-doped layer is used as the channel layer but also thecase where the channel layer is a usual n-type dopant layer.

Furthermore, the method described in this embodiment can be applied to alateral inversion-type MOSFET. FIG. 13 is a cross-sectional view showingthe configuration of lateral inversion-type MOSFETs. In FIG. 13, unlikeFIG. 11(b), a channel layer 74 (shown in FIG. 11(b)) is not formed. Theother structure of each MOSFET is the same as that in FIG. 11(b), andthus a description thereof is not given.

Other Embodiments

In the previously-described embodiments, a substrate having a surfacemiscut by approximately 8 degrees from 4H—SiC is used as a semiconductorsubstrate. However, in the present invention, any other substrate may beused as long as it has a surface inclined at an angle of 10 degrees orless from the designated crystal plane S in a predetermined direction A.

In the present invention, for example, a silicon carbide layerheteroepitaxially grown on a miscut Si substrate may be used.

In the previously-described embodiments, a 4H—SiC silicon carbide layeris used. However, in the present invention, a silicon carbide layer ofany other polytype crystal structure may be used as long as the polytypecrystal structure has characteristics that make the electron mobilitylarger in the direction perpendicular to the crystal plane than inin-plane directions of the crystal plane.

If a miscut substrate, in spite of a polytype crystal structure havingcharacteristics that make the electron mobility smaller in the directionperpendicular to the crystal plane than in in-plane directions of thecrystal plane has a possibility that the electron mobility becomeslarger in the miscut direction than in the direction perpendicular tothe miscut direction, this miscut substrate may be used.

In the previously-described embodiments, a semiconductor substratemiscut in the <11-20> direction is used as a 4H—SiC(0001) substrate.However, in the present invention, a substrate miscut in the <11-20>direction or the <1-100> direction may be used as a semiconductorsubstrate. In this case, when a silicon carbide layer is epitaxiallygrown on the semiconductor substrate, the top surface of the siliconcarbide layer is a plane miscut from the (0001) plane in the <11-20>direction or the <1-100> direction. However, as long as a desired planecomes to the top surface of the silicon carbide layer, the planeorientation and miscut direction of the semiconductor substrate locatedbelow the silicon carbide layer are not particularly restrictive. Inother words, as long as the longest of the edges of the source regionare configured to extend along the direction perpendicular to the miscutdirection, the miscut direction may be any other direction than thepreviously-mentioned miscut direction.

The (0001) plane of silicon carbide typically represents a siliconplane. However, a carbon plane represented as a (000-1) plane may beused instead of the (0001) plane.

Such a state that the electron mobility through silicon carbide becomeslarger in the miscut direction than in the other directions can beachieved when the interface state density at the interface between achannel region of a MOSFET and a gate insulating film thereof is 5×10¹²cm⁻²·eV⁻¹ or less at an energy level that is 0.1 eV smaller than theenergy level of the conduction band of silicon carbide. It is preferablethat the interface state density at the above-described interface is1×10¹² cm⁻²·eV⁻¹ or less. On the contrary, when the interface statedensity is larger than 5×10¹² cm⁻²·eV⁻¹, the influence of step-bunchingproduced at the above-described interface makes the electron mobilitysmaller in the miscut direction (perpendicular to the step-bunching)than in the direction parallel to the step-bunching like known siliconcarbide semiconductor devices.

In the previously-described embodiments, in order to reduce theinterface state density at the interface between the silicon carbidelayer and the gate insulating film, heat treatment is performed in anatmosphere containing nitric oxide (NO) after the formation of the gateinsulating film. However, in the present invention, the same effect canbe obtained by heat treatment in an atmosphere containing a group-Velement. If the interface state density can be reduced, heat treatmentmay be performed in any other atmosphere or any other processing methodmay be used.

In the previously-described embodiments, nickel or aluminum is used asan electrode material. However, in the present invention, the electrodematerial is not limited to these materials, and an electrode may have amultilayer structure.

In the fabrication method for a silicon carbide semiconductor device ofthe present invention, any method except for the fabrication methoddescribed in the embodiments may be used. Unless otherwise designated,conditions and gas types are not limited to those for the processdescribed herein. The silicon carbide semiconductor device may befabricated on any other conditions.

As a matter of course, the silicon carbide semiconductor device of thepresent invention can have various modifications as long as themodifications have the same principal structure within the scope of theinvention.

INDUSTRIAL APPLICABILITY

The semiconductor device of the present invention has a high industrialapplicability in that the electron mobility through a silicon carbidelayer, which has been reduced due to step-bunching or the otherunfavorable interface state, is improved, thereby achieving excellentelectrical characteristics.

1. A semiconductor device comprising: a semiconductor substrate; asilicon carbide layer formed on the semiconductor substrate and havingits top surface inclined at an angle of 10 degrees or less from acrystal plane in a miscut direction; a gate insulating film formed onthe silicon carbide layer; a gate electrode formed on the gateinsulating film; a source electrode formed on a part of the siliconcarbide layer located to a side of the gate electrode; a drain electrodeformed on the back surface of the semiconductor substrate; and a sourceregion formed in a region of the silicon carbide layer located at leastunder the source electrode, wherein the longest of the edges of thesource region extends along the direction perpendicular to the miscutdirection in a plan view, and the semiconductor device contains aV-group element at the interface between the silicon carbide layer andthe gate insulting film.
 2. The semiconductor device of claim 1, furthercomprising: a well region of a second conductivity type formed in a partof the silicon carbide layer located on a lateral side of the sourceregion and under the source region; and a base electrode electricallyconnected to the well region.
 3. The semiconductor device of claim 1,wherein a direction extending along the direction perpendicular to themiscut direction is a direction at an inclination of 5 degrees or lessfrom the direction perpendicular to the miscut direction.
 4. Thesemiconductor device of claim 1, wherein a channel layer is formed in aregion of the silicon carbide layer located under the gate insulatingfilm.
 5. The semiconductor device of claim 4, wherein the channel regionhas a multilayer structure including a first silicon carbide layer of atleast one layer and a second silicon carbide layer of at least one layerhaving a higher first-conductivity-type dopant concentration and asmaller thickness than the first silicon carbide layer.
 6. Thesemiconductor device of claim 1, wherein the electron mobility throughthe silicon carbide layer is larger in the direction perpendicular tothe crystal plane than in in-plane directions of the crystal plane. 7.The semiconductor device of claim 1, wherein the silicon carbide layeris 4H—SiC.
 8. The semiconductor device of claim 1, wherein the topsurface of the silicon carbide layer is a plane inclined from the (0001)plane in the <11-20> direction.
 9. The semiconductor device of claim 1,wherein the top surface of the silicon carbide layer is a plane inclinedfrom the (0001) plane in the <1-100> direction.
 10. The semiconductordevice of claim 1, wherein the gate insulating film is formed bythermally oxidizing the upper part of the silicon carbide layer andsubjecting the resultant upper part thereof to heat treatment in anatmosphere containing a compound inclusive of a group-V element.
 11. Thesemiconductor device of claim 10, wherein the compound inclusive of thegroup-V element is nitric oxide.
 12. The semiconductor device of claim10, wherein a maximum nitrogen concentration is 1×10²⁰ cm⁻³ through1×1022 cm⁻³ both inclusive at the interface between the silicon carbidelayer and the gate insulating film.
 13. The semiconductor device ofclaim 1, wherein the source electrode is formed using the sameconductive film as the base electrode.
 14. The semiconductor device ofclaim 1, wherein the gate electrode is formed to have a shape in whichpolygons are hollowed out in a plan view, and the longest of the edgesof the hollowed polygons extend along the direction perpendicular to themiscut direction.
 15. The semiconductor device of claim 14, wherein thesource electrode is formed in the shape of polygons in a plan view, andthe gate electrode is formed so as to be located apart from the sourceelectrode and surround the lateral sides of the source electrode. 16.The semiconductor device of claim 1, wherein the gate electrode isformed in the shape of a polygon in a plan view, and the longest of theedges of the polygon extends along the direction perpendicular to themiscut direction.
 17. The semiconductor device of claim 16, wherein in aplan view, the source electrode is formed to have a comb shape includinga plurality of first rectangular parts arranged in stripes and a firstconnection part through which the respective one ends of the pluralityof first rectangular parts are connected to one another, and the gateelectrode is formed to have a comb shape including a plurality ofstriped second rectangular parts arranged alternately with the pluralityof first rectangular parts and a second connection part through whichthe respective one ends of the plurality of second rectangular parts areconnected to one another.
 18. A semiconductor device comprising: asemiconductor substrate; a silicon carbide layer formed on thesemiconductor substrate and having its top surface inclined at an angleof 10 degrees or less from a crystal plane in a miscut direction; a gateinsulating film formed on the silicon carbide layer; a gate electrodeformed on the gate insulating film; a source electrode formed on a partof the silicon carbide layer located to one side of the gate electrode;a drain electrode formed on a part of the silicon carbide layer locatedto the other side of the gate electrode; and source/drain regions formedapart from each other in regions of the silicon carbide layer located atleast under the source and gate electrodes, wherein the opposed two ofthe edges of the source/drain regions extend along the directionperpendicular to the miscut direction in a plan view, and thesemiconductor device contains a V-group element at the interface betweenthe silicon carbide layer and the gate insulating film.
 19. Thesemiconductor device of claim 18, further comprising: a base regionformed in the silicon carbide layer and containing dopants of a firstconductivity type; and a base electrode electrically connected to thebase region.
 20. The semiconductor device of claim 18, wherein the gateelectrode is formed in the shape of a polygon, and the longest of theedges of the polygon extends along the direction perpendicular to themiscut direction.
 21. The semiconductor device of claim 18, wherein adirection extending along the direction perpendicular to the miscutdirection is a direction at an inclination of 5 degrees or less from thedirection perpendicular to the miscut direction.
 22. The semiconductordevice of claim 18, wherein a channel layer is formed in a region of thesilicon carbide layer located under the gate insulating film.
 23. Thesemiconductor device of claim 22, wherein the channel region has amultilayer structure including a first silicon carbide layer of at leastone layer and a second silicon carbide layer of at least one layerhaving a higher first-conductivity-type dopant concentration and asmaller thickness than the first silicon carbide layer.
 24. Thesemiconductor device of claim 18, wherein the electron mobility throughthe silicon carbide layer is larger in the direction perpendicular tothe crystal plane than in in-plane directions of the crystal plane. 25.The semiconductor device of claim 18, wherein the silicon carbide layeris 4H—SiC.
 26. The semiconductor device of claim 18, wherein the topsurface of the silicon carbide layer is a plane inclined from the (0001)plane in the <11-20> direction.
 27. The semiconductor device of claim18, wherein the top surface of the silicon carbide layer is a planeinclined from the (0001) plane in the <1-100> direction.
 28. Thesemiconductor device of claim 18, wherein the gate insulating film isformed by thermally oxidizing the upper part of the silicon carbidelayer and subjecting the resultant upper part thereof to heat treatmentin an atmosphere containing a compound inclusive of a group-V element.29. The semiconductor device of claim 28, wherein the compound inclusiveof the group-V element is nitric oxide.
 30. The semiconductor device ofclaim 28, wherein a maximum nitrogen concentration is 1×1020 cm−3through 1×1022 cm−3 both inclusive at the interface between the siliconcarbide layer and the gate insulating film.
 31. The semiconductor deviceof claim 18, wherein the source electrode is formed using the sameconductive film as the base electrode.